An Explicit Approach for Dynamic Power Evaluation for Deep Submicron Global Interconnects with Current Mode Signaling Technique

As the VLSI process technology is shrinking to the nanometer regime, power consumption of on-chip VLSI interconnects has become a crucial and an important issue. There are several methodologies proposed to estimate the on-chip power consumption using Voltage Mode Signaling technique (VMS). But the major drawback of VMS is that it increases the power consumption of on-chip interconnects compared to current mode signaling (CMS). A closed form formula is, thus, necessary for current mode signaling to accurately estimate the power dissipation in the distributed line. In this paper, we derived an explicit dynamic power formula in S-domain based on Modified Nodal Analysis (MNA) formulation. The usefulness of our approach is that dynamic power consumption of an interconnect line can be estimated accurately and efficiently at any operating frequency. By substituting s=0 in the vector of node voltages in our model results similar solution as that of Bashirullah et. al. Comparison of simulation results with other established models justifies the accuracy of our approach.